The present invention relates to an error-secure position measuring arrangement and method wherein a linked binary signal is generated from a plurality of binary scanning signals for error detection.
Error-secure position measuring devices are often used in processing machines to measure the relative position of a tool with respect to a workpiece that is to be processed and also in coordinate measuring machines for the determination of the position and/or the dimensions of a test object. The measuring device typically comprises a measuring scale and a scanning unit adapted to scan the measuring scale. The measuring scale is attached to one of the tool and workpiece and the scanning unit is attached to the other of the tool and workpiece. Relative movement between the tool and workpiece causes the scanning unit to move relative to the measuring scale and produce signals indicative of the relative position of the tool and workpiece.
Error security arrangements in incremental measuring systems are already known. Generally in these systems, unwanted interference pulses in the signal transmission channel are suppressed by transmitting the signals in complimentary form. The signals are transmitted as complimentary signals of like phase position on different channels to a signal receiver unit comprising a logic network. The logic network produces an output only when two complementary signals arrive simultaneously over both transmission channels (German published application AS No. 12 21 668). A disadvantage of this arrangement is that it is relatively complicated in construction since there must be two channels provided for each signal that is to be transmitted.
German patent DE-PS No. 20 22 151 describes an arrangement for the avoidance of errors in incremental measuring systems. The arrangement provides for the direct control of the mutual phase angle and amplitude levels of at least two scanning signals. The phase displaced scanning signals are fed simultaneously to an evaluating arrangement and to an error monitoring unit for the rectification of the scanning signals. A difference signal with a superposed constant threshold voltage is generated from the rectified scanning signals. If the difference signal falls below the threshold value, a flip-flop circuit responds to the sign of the difference signal, i.e. to the differential voltage zero, and triggers the error signal. This system has the disadvantage that it is not constructed in a manner secure against its own errors.
German document DE-OS No. 20 20 393 discloses an arrangement for error security in incremental measuring systems in which the control of the mutual phase angle and amplitude levels is performed directly on at least two scanning signals. Each of the scanning signals, phase displaced with respect to one another, is fed to a window trigger. The two window triggers, which have equal thresholds, generate output signals which drive a control circuit consisting of an AND-gate. The triggers are allocated to the middle ranges of the respective scanning signals. The AND-gate examines whether the switching states of the two window triggers coincide. If a coincidence is found, an error signal is produced. This arrangement also has the disadvantage that it is not constructed in a manner secure against its own errors.
From German patent DE-PS No. 22 07 224 there is known an error secured incremental position measuring arrangement in which a measuring graduation is scanned by a scanning device. The scanning device comprises four scanning units which generate four binary signals. The binary signals are phase displaced with respect to one another and each scanning unit comprises a scanning plate and an allocated photo-element. The scanning plate and photo-element are illuminated by an illuminating unit. A logic network, with known logic switching and linkage elements, generates a binary signal equal to a selected one of the four binary signals in response to an allowed combination of the binary signals. The allowed combination indicates an error free operation of the scanning units. A signal unequal to the selected binary signal is generated by the logic network in response to a forbidden combination of the binary signals. This condition indicates a faulty operation of the scanning units. The binary signal generated by the logic network and the selected binary signal are fed to respective counters. The outputs of the counters are compared by a comparator which is also responsive to a clock signal. If the counters are equal and the comparator is faultless, the comparator generates a signal. The signal indicates the faultless operation of the entire system and is equal in frequency to that of the clock signal. In addition to being applied to the comparator, the clock signal is also applied successively, and earlier in time, to a series of additional comparators. The additional comparators monitor the switching and linkage elements of the logic network for errors by checking, in each case, pairs of signals for equality. Although this arrangement is secure against its own errors, the arrangement is expensive, requiring two evaluating arrangements and two counters. In addition, the failure of the common illuminating unit for the four scanning units cannot always be recognized with the aid of the error signal.
It is an object of the present invention to provide an incremental position measuring arrangement of the type discussed above which is simply constructed and detects substantially all errors arising in actual practice.